All Wet ULSI manufacturing process
Most metal wiring used in ULSI is mostly made from a barrier layer and copper piping. The barrier layer is constructed to prevent the leakage of copper onto Si substrates. Today’s process rules call for efforts to create thinner and more compact chips of only a few nanometers in thickness. In addition, there is demand for super filling that does not cause any defects to arise within trenches, where we continue to see efforts to further compact and improve aspect ratios of copper fillings. There is also a need to fulfill the condition of enabling low cost processes within these structures.
This project proposes the creation of a barrier layer structure on top of a silicon substrate, low-k substrate, and polyimide substrate and then cooper wiring after that. The project aims to confirm that it is possible to shrink barrier film made with electroless plating to a thickness of 6 nm. Success has been made in embedding copper in a fine trench and constructing a protective layer using electroless and electro-plating.
The project relates to wiring and interconnection technology for wiring in ULSI, semiconductor packages, and signal transfers between electric circuits, and these can be applied to all differing order circuitry.
This technology is perfect for ULSI wiring, and it is possible to apply an all-wet method to the full execution of the wiring process. It is thought that there is a need for the construction of barrier film and the thinning of barriers when wiring within semiconductor packages and electric circuitry parts due to the miniaturization of these packages and circuitry parts. This technology allows for the use of ULSI technology without having to select substrate materials, making it useful for future technology.
purpose of providing seeds
Sponsord research, Collaboration research, Technical consultation
same researcher's seeds
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