To deal with the reliability issue caused by soft errors, a low power soft error hardened latch (SHC) design using Schmitt-Trigger-based C-element is proposed for reliable low power applications in this research.  The total number of transistors of the proposed SHC latch is only increased by 2 when compared to the conventional unhardened C2MOS latch, while up to 82.96% power reduction can be achieved when compared to the existing soft error tolerant HiPeR design.  When soft errors occur in the internal nodes of the proposed SHC, it can be filtered inside and will not cause the output Q to be upset.  Moreover, in case of soft errors occurring and affecting the output, the proposed SHC latch can recover to the correct state as fast as the existing works while they usually introduce about 2X area overhead as large as the proposed SHC, which clearly shows the effectiveness of the proposed low cost SHC design.