表題番号:2017K-191 日付:2018/04/06
研究課題高速かつ低電力なソフトエラー耐性をもつラッチの設計
研究者所属(当時) 資格 氏名
(代表者) 理工学術院 基幹理工学部 教授 柳澤 政生
研究成果概要
As semiconductor technology continues scaling down, the reliability issue has become much more critical than ever before.  Unlike traditional hard-errors caused by permanent physical damage which can’t be recovered in field, soft errors are caused by radiation or voltage/current fluctuations that lead to transient changes on internal node states, thus they can be viewed as temporary errors.  However, due to the unpredictable occurrence of soft errors, it is desirable to develop soft error tolerant designs.  For this reason, soft error tolerant design techniques have gained great research interest.  In this research, low-power soft error tolerant SHC latch is proposed using C-elements.  SHC latch and existing soft error tolerant latch are implemented and evaluated by spice simulator.  80.52% power reduction at maximum is achieved by SHC latch compared with HiPeR latch.  66.04% delay reduction at maximum is achieved by improved SHC latch compared with FERST latch.