Secure LSI is a key technology to protect growing IoT from hacking. In this research, its prime building blocks PUF (Physical Unclonable Function) and TRNG (True Random Number Generator) are focused. Device variation and noise plays important rolls in both circuits. To obtain fundamental data on them and to evaluate SRAM based PUF, a test chip has been designed in 180nm CMOS. The design data has been taped out to VDEC and is now under fabrication. The test chip consists of following circuits.
(1) nMOS and pMOS transistors array: Statistic data of devise variations and noises are obtained from this test circuit.
(2) SRAM based PUFs: Seven types of SRAM based PUFs are integrated on the chip. By comparing characteristics of them, effects of device variation and noise on operation stability will be made clear. This data can also be utilized to predict the randomness of TRNG.
  Furthermore, a new PUF circuit and a new TRNG circuit for stable operation and low power are thought-up, and their basic operations are verified by circuit simulations using SPICE.